Anti-Tamper Digital Clocks Options



Therefore, the current creation is just not intended to be limited to the embodiments proven herein but should be to be accorded the widest scope in keeping with the concepts and novel options disclosed herein.

using the clock to result in an Consider circuit that employs the plurality of delayed monotone indicators to detect a clock fault.

delaying the monotone signal employing each of the plurality of resettable hold off line segments to deliver a respective plurality of delayed monotone indicators Every possessing possibly a one or a zero logic value; and

A different hold off line phase could have N hold off things that generate the utmost delayed monotone sign 230-N. AND gates inside the delay traces might Each individual Have got a reset enter RST to reset the road concerning the hold off things to set the delay line to an Original acknowledged point out.

In other far more in-depth aspects of the creation, Just about every of your plurality of delayed monotone signals 230 might comprise either a a person or perhaps a zero. The Consider circuit 240 may determine no matter if the volume of kinds while in the plurality of delayed monotone indicators differs from the h2o amount variety by in excess of a predetermined threshold.

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Resettable delay line segments between a resettable hold off line segment connected to a least delay time along with a resettable hold off line phase linked to a most check here delay time are each related to discretely expanding hold off situations. The Assess circuit is induced because of the clock and uses the plurality of delayed monotone alerts to detect a clock fault.

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nine. The apparatus for detecting clock tampering as outlined in claim 8, additional comprising: means for resetting the implies for delaying the monotone sign during a reset period of time, whereby the reset period of time is before the clock evaluate period of time.

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24. The strategy for detecting voltage tampering as outlined in claim 23, additional comprising: resetting the resettable delay line segments in the course of a reset period of time, wherein the reset time period is prior to the evaluate time period.

eleven. The apparatus for detecting clock tampering as described in claim eight, wherein-the implies for analyzing establishes no matter whether the amount of types from the plurality of delayed monotone indicators differs from the water amount amount by greater than a predetermined threshold.

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employing a clock to cause an evaluate circuit that takes advantage of the plurality of delayed monotone alerts to detect a voltage fault.

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